1. Field of the Invention
The invention generally relates to dual-strain layers for mechanical stress control to improve charge carrier mobility, and, more particularly, to an improved dual-strain layer that enhances carrier mobility in digital circuits and simultaneously minimizes variability in static random access memory (SRAM) arrays and/or analog field effect transistors (FETs) on the same substrate.
2. Description of the Related Art
The mobility of the charge carriers through the channel region a metal oxide semiconductor field effect transistor (MOSFET) directly affects MOSFET performance. Specifically, carrier mobility affects the amount of current or charge which flows, e.g., as electrons or holes, in the MOSFET channel region. Reduced carrier mobility can reduce the switching speed of a given transistor. Reduced carrier mobility can also reduce the differences between the on and off states and can, therefore, increase susceptibility to noise. Various techniques have been used to improve the charge carrier mobility in such devices. For example, mechanical stress control of the channel regions can be used to enhance hole mobility p-type MOSTFETs (p-FETs) and electron mobility n-type MOSFETs (n-FETs). Specifically, forming a compressive film over a p-FET structure causes enhances hole mobility to optimize p-FET performance. Alternatively, forming a tensile film over an n-FET structure enhances electron mobility to optimize p-FET performance. Thus, state-of-the-art complementary MOSFET (CMOS) devices and other semiconductor structures in which both n-FETs and p-FETs are formed on the same chip often incorporate a dual-strain nitride layer to enhance mobility in both the n-FETs and the p-FETs. Such a dual-strain nitride layer is a nitride layer that has tensile strain regions and compressive strain regions positioned over the n-FETs and the p-FETs, respectively, in order to simultaneously enhance carrier mobility in the channel regions of each of the FETs.
Various masking and physical overlay processes can be used to place the different strain regions and, thus, to form the dual-strain nitride layer such that the boundaries between the different strain regions fall between the n-FETs and p-FETs. However, since a physical overlay is involved in the placement of the different strain regions, there can be significant variability in the nFET and pFET resultant strains depending on the proximity of the individual FETs to this boundary. As a result, there can be an increased variability in the transconductance of such transistors. While this increased transconductance variability may not significantly affect digital logic performance, it can lead to a decrease static random access memory (SRAM) cell stability and performance. Such transconductance variability can also negatively affect the stability and performance of analog FETs. Thus, there is a need for a semiconductor structure that balances carrier mobility enhancement with transconductance variability in order to optimize device stability and performance.